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dc.contributor.authorColodro Conde, Carlos es_ES
dc.contributor.authorToledo Moreo, Rafael es_ES
dc.date.accessioned2016-04-07T11:41:52Z
dc.date.available2016-04-07T11:41:52Z
dc.date.issued2015-10
dc.identifier.citationCOLODRO CONDE, Carlos, TOLEDO MOREO, Rafael. Design and analysis of efficient synthesis algorithms for EDAC functions in FPGAs. En: IEEE Transactions on Aerospace and Electronic Systems, vol. 51, n. 4, p. 3332 - 3347, 2015. ISSN: 0018-9251es_ES
dc.identifier.issn0018-9251
dc.description.abstractError Detection and Correction (EDAC) functions have been widely used for protecting memories from single event upsets (SEU), which occur in environments with high levels of radiation or in deep submicron manufacturing technologies. This paper presents three novel synthesis algorithms that obtain areaefficient implementations for a given EDAC function, with the ultimate aim of reducing the number of sensitive configuration bits in SRAM-based Field-Programmable Gate Arrays (FPGAs). Having less sensitive bits results in a lower chance of suffering a SEU in the EDAC circuitry, thus improving the overall reliability of the whole system. Besides minimizing area, the proposed algorithms also focus on improving other figures of merit like circuit speed and power consumption. The executed benchmarks show that, when compared to other modern synthesis tools, the proposed algorithms can reduce the number of utilized look-up tables (LUTs) up to a 34.48%. Such large reductions in area usage ultimately result in reliability improvements over 10% for the implemented EDAC cores, measured as MTBF (Mean Time Between Failures). On the other hand, maximum path delays and power consumptions can be reduced up to a 17.72% and 34.37% respectively on the placed and routed designs.es_ES
dc.description.sponsorshipThis work was supported by the Spanish Ministry of Educacion, Cultura y Deporte under the grant FPU12/05573, and by the Spanish Ministry of Economıa project ESP2013-48362-C2-2-P, in the frame of the activities of the Instrument Control Unit of the Infrarred Instrument of the ESA Euclid Mission carried out by the Dept. of Electronics and Computer Technology of the Universidad Politécnica de Cartagenaes_ES
dc.formatapplication/pdfes_ES
dc.language.isoenges_ES
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)es_ES
dc.relationContributions to technology and techniques for ground-based and space-based astronomy synthesis of EDAC codecs, AOLI and COELI.
dc.relation.urihttp://hdl.handle.net/10317/6672es_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights© Copyright 2015 IEEEes_ES
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.titleDesign and analysis of efficient synthesis algorithms for EDAC functions in FPGAses_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.subjectField programmable gate arrays (FPGA)es_ES
dc.subjectSynthesis toolses_ES
dc.subjectEfficient synthesises_ES
dc.subjectError detection and correction (EDAC)es_ES
dc.subjectSingle event upsets (SEU)es_ES
dc.identifier.urihttp://hdl.handle.net/10317/5326
dc.peerreviewSies_ES
dc.identifier.doi10.1109/TAES.2015.140823
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES
dc.type.versioninfo:eu-repo/semantics/submittedVersiones_ES
dc.relation.projectIDESP2013-48362-C2-2-Pes_ES
dc.relation.projectIDFPU12/05573es_ES
dc.subject.unesco1206.01 Construcción de Algoritmoses_ES
dc.contributor.funderMinisterio de Educación, Cultura y Deportees_ES
dc.contributor.funderMinisterio de Economía, Industria y Competitividades_ES


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