TY - JOUR 
A1 - Díaz Madrid, José Ángel
AU - Doménech Asensi, Ginés
AU - Martínez Álvarez, José Javier
AU - Zapata Pérez, Juan Francisco
AU - Ruiz Merino, Ramón Jesús
T1 - Joint implementation of the sharing OTA and bias current regulation techniques in a 11-bit 10 MS/s pipelined ADC
Y1 - 2020
UR - http://hdl.handle.net/10317/8774
AB - The power dissipation of a pipeline analog to digital converter (ADC) depends on different design
strategies. In this brief communication, an 11-bit pipeline ADC consisting of five stages with 2.5
effective bit resolution is described. The circuit combines two main techniques to improve power
dissipation, such as sharing OTAs between adjacent ADC stages and dynamic regulation of the OTA
biasing according to the stage and subcycle of operation. To reduce the charge injection effect caused
by the OTA sharing added circuitry, the ADC uses a topology based on four-input OTAs to reduce
the number of transmission gates. The ADC has been fabricated using a standard 0.35 µm CMOS
process. It consumes 17.85 mW at 10 MSample/s sampling rate. With this resolution and sampling
rate, the measurement results show that it achieves 58.20 dB SNDR and 9.38 bit ENOB at 1 MHz
input frequency.
KW - Electrónica
KW - Analog-to-digital converter (ADC)
KW - Op-amp sharing
KW - Bias current regulation
KW - Low power
LA - eng
PB - Springer Nature
ER -