TY - JOUR 
A1 - Díaz Madrid, José Ángel
AU - Doménech Asensi, Ginés
AU - Ruiz Merino, Ramón Jesús
AU - Zapata Pérez, Juan Francisco
AU - Martínez Álvarez, José Javier
T1 - Mixed signal multiply and adder parallel circuit for  deep learning convolution operations
Y1 - 2020
SN - 2158-1525
UR - http://hdl.handle.net/10317/10371
AB - This work presents a new analog architecture to perform image convolution for deep learning purposes in CMOS 
imagers in the analog domain. The architecture is focused to reduce both power dissipation and data transfer between memory and the analog operators. It uses mixed signal multiply and add operators arranged following a row-parallel architecture in order to be fully scalable for different CMOS imager sizes. The multiplier circuit used is based on a current mode architecture to multiply the value of analog inputs by the digital stored weights and produce current mode outputs which are then added to obtain the 
convolution result. A digital control circuit manages the pixel readout and the multiply and add operations. The architecture is 
demonstrated performing 3x3 convolutions on 64x64 images with a padding equal to 1. Convolution weights are locally stored as 4-bit digital values. The circuit has been synthesized in 110 nm CMOS technology. For this configuration, the simulation results show that the circuit is able to perform a whole convolution in 32 us and achieve an efficiency of 2.13 TOPS/W. These results can be extrapolated to larger CMOS imagers and different mask sizes.
KW - Electrónica
KW - Multiplier
KW - CMOS
KW - Computer vision
KW - Deep neural network
LA - eng
PB - IEEE
ER -