Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current
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Díaz Madrid, José Ángel; Doménech Asensi, Ginés; Ruiz Merino, Ramón Jesús; Zapata Pérez, Juan Francisco; Martínez Álvarez, José JavierGrupo de investigación
Desarrollo de sistemas y circuitos electrónicos y microelectrónicosÁrea de conocimiento
ElectrónicaPatrocinadores
This work has been partially funded by Spanish Ministerio de Ciencia e Innovación (MCI), Agencia Estatal de Investigación (AEI) and European Region Development Fund (ERDF/FEDER) under grant RTI2018-097088-B-C33Realizado en/con
Universidad Politécnica de CartagenaFecha de publicación
2020-07-01Editorial
Springer NetherlandsCita bibliográfica
Díaz-Madrid, J.Á., Doménech-Asensi, G., Ruiz-Merino, R. et al. Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current. Analog integrated circuits and signal processing 105, 45–55 (2020). https://doi.org/10.1007/s10470-020-01700-2Palabras clave
Analog-to-digital converter (ADC)CMOS
OTA
Low power
Adaptive bias current
Resumen
This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 µW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.
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