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dc.contributor.authorDíaz Madrid, José Ángel 
dc.contributor.authorHauer, Hans 
dc.contributor.authorDoménech Asensi, Ginés 
dc.date.accessioned2009-03-26T07:54:31Z
dc.date.available2009-03-26T07:54:31Z
dc.date.issued2009-03-26T07:54:31Z
dc.identifier.issn1698-2924
dc.description.abstractThree 12 bit, 40 MS/s pipelined analog-to-digital-converters (ADCs) are developed in 0.35μm CMOS process with 3.3V single power supply. The proposed ADCs architectures study the influence of the amplifier sharing technique in the power consumption and the main performances in the pipeline ADCs. Simulations results with extracted netlists are provided and show that the amplifier sharing technique has potential to be used in the reduction of the power consumption.es
dc.description.sponsorshipThis work has been partially supported by Ministerio de Educación y Ciencia of Spain (TIN2006-15460-C04-04).es
dc.formatapplication/pdf
dc.language.isoenges
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.titleInfluence of the amplifier sharing tecnique in pipeline analog-to digital converters (ADCs)es
dc.typeinfo:eu-repo/semantics/articlees
dc.subjectConvertidores digitaleses
dc.subjectAmplificadores analógicoses
dc.identifier.urihttp://hdl.handle.net/10317/873
dc.contributor.investgroupGrupo Diseño Electronico y Técnicas de Tratamiento de Señales
dc.rights.accessRightsinfo:eu-repo/semantics/openAccess


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Atribución-NoComercial-SinDerivadas 3.0 España
Except where otherwise noted, this item's license is described as Atribución-NoComercial-SinDerivadas 3.0 España