Optimizing the design of single-stage power factor correctors
Research Group
División de Sistemas e Ingeniería Electrónica (DSIE)Knowledge Area
Tecnología ElectrónicaPublication date
2007-06Publisher
IEEE Industrial Electronics SocietyBibliographic Citation
VILLAREJO , José A., SEBASTIAN, Javier, SOTO, Fulgencio, JÓDAR, Esther de. Optimizing the design of single-stage power factor correctors. IEEE Transactions on Industrial Electronics , 54 (3): 1472-1482, Junio 2007. ISSN 0278-0046Keywords
Armónicos actualesNormas IEC 61000-3-2
Cargas no lineales
Corrección del factor de potencia (PFC)
Abstract
This paper presents a new analytical method for the
generalized study of a cluster of single-stage power-factor correctors
(S2PFCs). Due to this generalized approach, new topologies
have been obtained, and the study of other known topologies has
been simplified. The new analytical method simplifies the design
of S2PFCs by making it possible to compare a large number of
different designs from the same viewpoint in order to identify the
best topology. Finally, this research has enabled us to reduce the
total size of the additional inductors that are used by a factor of
two to three with respect to previous implementations.
Collections
- Artículos [1753]
The following license files are associated with this item:
Social media