Mixed signal multiply and adder parallel circuit for deep learning convolution operations
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Díaz Madrid, José Ángel; Doménech Asensi, Ginés; Ruiz Merino, Ramón Jesús; Zapata Pérez, Juan Francisco; Martínez Álvarez, José JavierGrupo de investigación
Desarrollo de sistemas y circuitos electrónicos y microelectrónicosÁrea de conocimiento
ElectrónicaPatrocinadores
This work has been partially funded by Spanish government through project RTI2018-097088-B-C33 (MINECO/FEDER, UE)Fecha de publicación
2020-10-31Editorial
IEEECita bibliográfica
DÍAZ MADRID, José Ángel et al. Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. En: IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180757.Revisión por pares
SíPalabras clave
MultiplierCMOS
Computer vision
Deep neural network
Resumen
This work presents a new analog architecture to perform image convolution for deep learning purposes in CMOS
imagers in the analog domain. The architecture is focused to reduce both power dissipation and data transfer between memory and the analog operators. It uses mixed signal multiply and add operators arranged following a row-parallel architecture in order to be fully scalable for different CMOS imager sizes. The multiplier circuit used is based on a current mode architecture to multiply the value of analog inputs by the digital stored weights and produce current mode outputs which are then added to obtain the
convolution result. A digital control circuit manages the pixel readout and the multiply and add operations. The architecture is
demonstrated performing 3x3 convolutions on 64x64 images with a padding equal to 1. Convolution weights are locally stored as 4-bit digital values. The circuit has been synthesized in 110 nm CMOS technology. For this configuration, the simulation ...
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