TY - JOUR 
A1 - Díaz Madrid, José Ángel
AU - Doménech Asensi, Ginés
AU - Ruiz Merino, Ramón Jesús
AU - Zapata Pérez, Juan Francisco
AU - Martínez Álvarez, José Javier
T1 - Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current
Y1 - 2020
SN - 1573-1979
UR - http://hdl.handle.net/10317/8768
AB - This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 µW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.
KW - Electrónica
KW - Analog-to-digital converter (ADC)
KW - CMOS
KW - OTA
KW - Low power
KW - Adaptive bias current
KW - 2203.01 Circuitos
LA - eng
PB - Springer Netherlands
ER -