TY - JOUR
A1 - Doménech Asensi, Ginés
AU - Kazmierski, Tom J.
T1 - High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors
Y1 - 2019
SN - 1558-1101
UR - http://hdl.handle.net/10317/8760
AB - This work describes a high-speed simulation technique of analog circuits which is based on the use of statespace equations and an explicit integration method parallelised on a multiprocessor architecture. The integration step of
such method is smaller than the one required by an implicit simulation technique based on Newton–Raphson iterations.
However, given that explicit methods do not require the computation of time-consuming matrix factorizations, the overall
simulation time is reduced. The technique described in this work has been implemented on a NVIDIA general purpose
GPU and has been tested simulating the Gaussian filtering operation performed by a smart CMOS image sensor. Such
devices are used to perform computation on the edge and include built-in image processing functions. Among those, the
Gaussian filtering is one of the most common functions, since it is a basic task for early vision processing. These smart
sensors are increasingly complex and hence the time required to simulate them during their design cycle is also larger
and larger. From a certain imager size, the proposed simulation method yields simulation times two order of magnitude
faster that an implicit method based tool such us SPICE
KW - Simulation acceleration
KW - State-space technique
KW - Many-core
KW - GPU
KW - CMOS imager
KW - Electrónica
KW - 3325 Tecnología de las Telecomunicaciones
LA - eng
PB - IEEE
ER -