TY - JOUR 
A1 - Neubauer, Harald
AU - Doménech Asensi, Ginés
AU - Ruiz Merino, Ramón Jesús
AU - Díaz Madrid, José Ángel
T1 - Comparative analysis of two operational  amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS
Y1 - 2008
UR - http://hdl.handle.net/10317/1255
AB - This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for low power dissipation. All analog components of this pipeline ADC are fully differential, as there are dynamic comparators, analog multiplexers and operational amplifiers with gain boosting.
KW - Electrónica
KW - ADC
KW - CMOS
KW - Amplificadores operacionales
KW - Fuentes de información
KW - Operational amplifier
KW - Pipeline
LA - eng
PB - Institute Electrical and Electronics Engineers (IEEE)
ER -