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dc.contributor.authorDíaz Madrid, José Ángel 
dc.contributor.authorDoménech Asensi, Ginés 
dc.contributor.authorMartínez Álvarez, José Javier 
dc.contributor.authorZapata Pérez, Juan Francisco 
dc.contributor.authorRuiz Merino, Ramón Jesús 
dc.date.accessioned2020-10-02T09:52:06Z
dc.date.available2020-10-02T09:52:06Z
dc.date.issued2020-07-01
dc.identifier.citationDíaz-Madrid, J.Á., Doménech-Asensi, G., Martínez-Álvarez, J.J. et al. Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. Circuits Syst Signal Process (2020). https://doi.org/10.1007/s00034-020-01493-9es_ES
dc.description.abstractThe power dissipation of a pipeline analog to digital converter (ADC) depends on different design strategies. In this brief communication, an 11-bit pipeline ADC consisting of five stages with 2.5 effective bit resolution is described. The circuit combines two main techniques to improve power dissipation, such as sharing OTAs between adjacent ADC stages and dynamic regulation of the OTA biasing according to the stage and subcycle of operation. To reduce the charge injection effect caused by the OTA sharing added circuitry, the ADC uses a topology based on four-input OTAs to reduce the number of transmission gates. The ADC has been fabricated using a standard 0.35 µm CMOS process. It consumes 17.85 mW at 10 MSample/s sampling rate. With this resolution and sampling rate, the measurement results show that it achieves 58.20 dB SNDR and 9.38 bit ENOB at 1 MHz input frequency.es_ES
dc.description.sponsorshipThis work has been partially funded by Spanish Ministerio de Ciencia e Innovaci´on (MCI), Agencia Estatal de Investigaci´on (AEI) and European Region Development Fund (ERDF/FEDER) under grant RTI2018-097088-BC33es_ES
dc.formatapplication/pdfes_ES
dc.language.isoenges_ES
dc.publisherSpringer Naturees_ES
dc.relation.urihttps://doi.org/10.1007/s00034-020-01493-9es_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.titleJoint implementation of the sharing OTA and bias current regulation techniques in a 11-bit 10 MS/s pipelined ADCes_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.subjectAnalog-to-digital converter (ADC)es_ES
dc.subjectOp-amp sharinges_ES
dc.subjectBias current regulationes_ES
dc.subjectLow poweres_ES
dc.subject.otherElectrónicaes_ES
dc.identifier.urihttp://hdl.handle.net/10317/8774
dc.peerreviewes_ES
dc.contributor.investgroupDesarrollo de sistemas y circuitos electrónicos y microelectrónicoses_ES
dc.identifier.doi10.1007/s00034-020-01493-9
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_ES
dc.relation.projectIDRTI2018-097088-B-C33es_ES
dc.contributor.funderRTI2018-097088-B-C33 (MCI/AEI/FEDER, UE)es_ES


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Except where otherwise noted, this item's license is described as Atribución-NoComercial-SinDerivadas 3.0 España