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dc.contributor.authorDoménech Asensi, Ginés 
dc.contributor.authorKazmierski, Tom J. 
dc.date.accessioned2020-09-21T11:45:06Z
dc.date.available2020-09-21T11:45:06Z
dc.date.issued2019-09-01
dc.identifier.citationG. Domenech-Asensi and T. J. Kazmierski, "High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors," 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2020, pp. 646-64es_ES
dc.identifier.issn1558-1101
dc.description.abstractThis work describes a high-speed simulation technique of analog circuits which is based on the use of statespace equations and an explicit integration method parallelised on a multiprocessor architecture. The integration step of such method is smaller than the one required by an implicit simulation technique based on Newton–Raphson iterations. However, given that explicit methods do not require the computation of time-consuming matrix factorizations, the overall simulation time is reduced. The technique described in this work has been implemented on a NVIDIA general purpose GPU and has been tested simulating the Gaussian filtering operation performed by a smart CMOS image sensor. Such devices are used to perform computation on the edge and include built-in image processing functions. Among those, the Gaussian filtering is one of the most common functions, since it is a basic task for early vision processing. These smart sensors are increasingly complex and hence the time required to simulate them during their design cycle is also larger and larger. From a certain imager size, the proposed simulation method yields simulation times two order of magnitude faster that an implicit method based tool such us SPICEes_ES
dc.description.sponsorshipThis work has been partially funded by Spanish government through project RTI2018-097088-B-C33 (MINECO/FEDER, UE) and by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1. The research stay at University of Southampton (UK) has been supported by Ministerio de Educación, Cultura y Deporte within the “Programa Estatal de Promoción del Talento y su Empleabilidad en I+D+i, Subprograma Estatal de Movilidad, del Plan Estatal de I+D+I” under grant PRX18/00565.es_ES
dc.formatapplication/pdfes_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.relation.urihttp://www.doi.org/10.23919/DATE48585.2020.9116270es_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.titleHigh-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processorses_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.subjectSimulation accelerationes_ES
dc.subjectState-space techniquees_ES
dc.subjectMany-corees_ES
dc.subjectGPUes_ES
dc.subjectCMOS imageres_ES
dc.subject.otherElectrónicaes_ES
dc.identifier.urihttp://hdl.handle.net/10317/8760
dc.peerreviewSies_ES
dc.contributor.investgroupDesarrollo de sistemas y circuitos electrónicos y microelectrónicoses_ES
dc.identifier.doi10.23919/DATE48585.2020.9116270
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_ES
dc.relation.projectIDRTI2018-097088-B-C33es_ES
dc.subject.unesco3325 Tecnología de las Telecomunicacioneses_ES
dc.contributor.convenianteUniversity of Southampton (UK)es_ES
dc.contributor.funderMinisterio de Economía, Industria y Competitividades_ES
dc.contributor.funderFondo Europeo de Desarrollo Regional‏es_ES
dc.contributor.funderComisión Europeaes_ES
dc.contributor.funderEngineering and Physical Sciences Research Counciles_ES


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