Real time architectures for the scale Invariant feature transform algorithm
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AuthorDoménech Asensi, Ginés; Garrigós Guerrero, Francisco Javier; López Martínez, Paula; Brea Sánchez, Víctor Manuel; Cabello Ferrer, Diego
SponsorsThis work has been partially funded by Spanish government projects TEC2015-66878-C3-2-R (MINECO/FEDER, UE) and TEC2015- 66878-C3-3-R (MINECO/FEDER, UE).
PublisherVDE Verlag GmbH
Bibliographic CitationDoménech Asensi, Ginés et al. Real time architectures for the scale Invariant feature transform algorithm. En: CNNA 2016. (15º. 2016.); 15th International Workshop on Cellular Nanoscale Networks and their Applications: 23-25 Aug. 2016. Berlin: VDE Verlag GmbH 2016.p. 75-76. ISBN: 978-3-8007-4252-3
Scale invariant feature transform
Feature extraction in digital image processing is a very intensive task for a CPU. In order to achieve real time image throughputs, hardware parallelism must be exploited. The speed-up of the system is constrained by the degree of parallelism of the implementation and this one at the same time, by programmable device size and the power dissipation. In this work, issues related to the synthesis of the Scale-Invariant Feature Transform (SIFT) algorithm on a FPGA to obtain target processing rates faster than 50 frames per second for VGA images, are analyzed. In order to increase the speedup of the algorithm, the work includes the analysis of feasible simplifications of the algorithm for a tracking application and the results are synthesized on an FPGA.
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