Simulation-based low-level optimization tool for analog integrated circuits
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Research GroupDispositivos y Diseño Microelectrónico; Diseño Electrónico y Técnicas de Tratamiento de Señales
SponsorsThis work has been supported by Fundación Séneca of Región de Murcia and Ministerio de Ciencia y Tecnología od Spain, under grants PB/63/FS/02 and TIC2003-09400-C04-02, respectively.
Bibliographic CitationDOMÉNECH ASENSI, Ginés, LÓPEZ ALCANTUD, José Alejandro, RUIZ MERINO, Ramón. Simulation-based low-level optimization tool for analog integrated circuits. En: VLSI Circuits and Systems II (2005: Sevilla). Proceedings of SPIE: VLSI Circuits and Systems II. Sevilla. 2005. vol. 5837, 685-692 p. ISBN 9780819458322
KeywordsAutomatización de diseño electrónico
Circuito de optimización
CMOS analog integrated circuits
Electronic design automation
Circuitos integrados analógicos CMOS
In this paper, a tool based on free software to perform low level optimization on analog designs is presented. Nowadays, the use of design automation tools for microelectronic circuits design is extending from digital to analog circuits, due in part to the fact although the analog part of a mixed signal ASIC takes only the 10% of the silicona area, it represents almost 90% of the whole design time. For analog circuits, design process can be divided in two major tasks: topology selection an device sizing. The tool here presented consists on a simulation based optimizer, which is used to perform automatic low level analog circuit sizing. The tool is composed of three modules: a layout generator, which includes a parasitic extractor, an analog circuit simulator and circuit optimizer. The two first modules are respectively Mgic and Spice from Berkeley, while the third one, the optimizer, has been developed to evaluate dc, ac, and transient sensitivity simulations performed by Spice and make ...
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