TY - JOUR 
A1 - Doménech Asensi, Ginés
AU - Ruiz Merino, Ramón Jesús
AU - Zapata Pérez, Juan Francisco
AU - López Alcantud, José Alejandro
AU - Díaz Madrid, José Ángel
T1 - FPGA synthesis of an stereo image matching architecture for autonomous mobile robots
Y1 - 2017
UR - http://hdl.handle.net/10317/6605
AB - This paper describes a hardware proposal to speed up the process of image matching in stereo vision systems like those employed by autonomous mobile robots. This proposal combines a classical window-based matching approach with a previous stage, where key points are selected from each image of the stereo pair. In this first step the key point extraction method is based on the SIFT algorithm. Thus, in the second step, the window-based matching is only applied to the set of selected key points, instead of to the whole images. For images with a 1% of key points, this method speeds up the matching four orders of magnitude. This proposal is, on the one hand, a better parallelizable architecture than the original SIFT, and on the other, a faster technique than a full image windows matching approach. The architecture has been implemented on a lower power Virtex 6 FPGA and it achieves a image matching speed above 30 fps.
KW - Electrónica
KW - Computer vision
KW - Stereo vision
KW - SIFT
KW - SAD
KW - FPGA
KW - 2203 Electrónica
LA - eng
ER -