TY - JOUR 
A1 - Doménech Asensi, Ginés
AU - Garrigós Guerrero, Francisco Javier
AU - López Martínez, Paula
AU - Brea Sánchez, Víctor Manuel
AU - Cabello Ferrer, Diego
T1 - Real time architectures for the scale Invariant  feature transform algorithm
Y1 - 2017
UR - http://hdl.handle.net/10317/6604
AB - Feature extraction in digital image processing is a very intensive task for a CPU. In order to achieve real time image throughputs, hardware parallelism must be exploited. The speed-up of the system is constrained by the degree of parallelism of the implementation and this one at the same time, by programmable device size and the power dissipation. In this work, issues related to the synthesis of the Scale-Invariant Feature Transform (SIFT) algorithm on a FPGA to obtain target processing rates faster than 50 frames per second for VGA images, are analyzed. In order to increase the speedup of the algorithm, the work includes the analysis of feasible simplifications of the algorithm for a tracking application and the results are synthesized on an FPGA.
KW - FPGA
KW - VHDL
KW - Scale invariant feature transform
KW - 2209.90 Tratamiento Digital. Imágenes
LA - eng
PB - VDE Verlag GmbH
ER -