A low kickback fully differential dynamic comparator for pipeline analog-to-digital converters
Área de conocimiento
ElectrónicaPatrocinadores
This work has been partially funded by Spanish government projects TEC2015‐66878‐C3‐2‐R (MINECO/FEDER, UE) and RTI2018‐097088‐B‐C33 (MINECO/FEDER, UE).Realizado en/con
Fraunhofer Institute IIS; Universidad Politécnica de CartagenaFecha de publicación
2019-11-10Editorial
John Wiley & Sons LtdCita bibliográfica
Diaz-Madrid J-A, Domenech-Asensi G, Hauer J, Mateu L. A low kickback fully differential dynamic comparator for pipeline analog-to-digital converters. Engineering Reports. 2019;e12055. https://doi.org/10.1002/eng2.12055Revisión por pares
SíPalabras clave
ADCAnalog circuit
Complementary metal-oxide-semiconductor,
Dynamic comparator
Resumen
This study presents a fully differential dynamic comparator with low kickback noise, an effect caused by voltage variations in the regeneration nodes of these types of circuit. Given their low power dissipation, dynamic comparators are key circuits in analog-to-digital converters (ADCs), especially in pipelined ADCs. The proposed comparator has been simulated and compared with three other comparator topologies. The value of the kickback noise generated by the proposed circuit is lower than that generated by other conventional dynamic comparators over a wide input range, while simultaneously showing a low offset voltage error. The dynamic comparator has been implemented in a low-resolution ADC with a resolution of 2.5 effective bits, which has been
prototyped in a 0.35-𝜇m CMOS AMS C35B4 process. Its size is 34 𝜇m × 38 𝜇m.
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