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dc.contributor.authorDoménech Asensi, Ginés 
dc.contributor.authorKazmierski, Tom J. 
dc.date.accessioned2020-01-23T13:18:19Z
dc.date.available2020-01-23T13:18:19Z
dc.date.issued2019-09-03
dc.identifier.citationG. Doménech-Asensi and T. J. Kazmierski, "Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors," 2019 Forum for Specification and Design Languages (FDL), Southampton, United Kingdom, 2019, pp. 1-4. doi: 10.1109/FDL.2019.8876903es_ES
dc.identifier.issn1636-9874
dc.description.abstractThis paper describes an efficient numerical solution to speed up transient simulations of analog circuits on a many-core computer. The technique is based on an explicit integration method, parallelised on a multiprocessor architecture. Although the integration step is smaller than the required one by traditional simulation methods based on Newton–Raphson iterations, explicit methods do not require to compute complex calculations such us matrix factorizations, which lead to long CPU simulation times. The proposed technique has been implemented on a NVIDIA GPU and has been demonstrated simulating Gaussian filtering operations performed by a CMOS vision chip. These type of devices, which are used to perform computation on the edge, include built-in image processing functions, turning them into very complex and time consuming circuits during their design. The proposed method is faster that Ngspice for different image sizes, and for 128 x 128 pixels image size it achieves a speed up of two orders of magnitude.es_ES
dc.description.sponsorshipThis work has been partially funded by Spanish government through project RTI2018-097088-B-C33 and by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1. The research stays at University of Southampton (UK) have been supported by Ministerio de Educación, Cultura y Deporte within the “Programa Estatal de Promoción del Talento y su Empleabilidad en I+D+i, Subprograma Estatal de Movilidad, del Plan Estatal de I+D+I” under grant PRX18/00565 and by Universidad Politécnica de Cartagena - Campus de Excelencia Internacional Mare Nostrumes_ES
dc.formatapplication/pdfes_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.titleSimulation acceleration of image filtering on CMOS vision chips using many-core processorses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.subjectCMOS vision chipes_ES
dc.subjectGPUes_ES
dc.subjectState-space techniquees_ES
dc.subjectSimulation accelerationes_ES
dc.subject.otherElectrónicaes_ES
dc.identifier.urihttp://hdl.handle.net/10317/8331
dc.peerreviewSi
dc.identifier.doi10.1109/FDL.2019.8876903
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES
dc.relation.projectIDRTI2018-097088-B-C33es_ES
dc.contributor.convenianteUniversity of Southampton (UK)es_ES
dc.contributor.funderMinisterio de Educación, Cultura y Deportees_ES
dc.contributor.funderUniversidad Politécnica de Cartagenaes_ES
dc.contributor.funderEngineering and Physical Sciences Research Counciles_ES
dc.contributor.funderUniversity of Southamptones_ES


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Except where otherwise noted, this item's license is described as Atribución-NoComercial-SinDerivadas 3.0 España