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dc.contributor.authorRubio Ibáñez, Pablo 
dc.contributor.authorMartínez Álvarez, José Javier 
dc.contributor.authorDoménech Asensi, Ginés 
dc.date.accessioned2020-01-22T09:18:47Z
dc.date.available2020-01-22T09:18:47Z
dc.date.issued2019-05-28
dc.identifier.citationP. Rubio-Ibáñez, J. J. Martínez-Álvarez and G. Doménech-Asensi, "Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702453es_ES
dc.identifier.issn2158-1525
dc.description.abstractThis paper describes the design and the implementation of a high-performance area-efficient upscaling function on a FPGA. The proposed function performs the resizing of real time video images, from M x N pixels to 2M x 2N pixels, using a bilinear interpolation method. The hardware implementation has been carried out using an RTL structural description in VHDL, to maximize the use of the specific resources of the FPGA, especially its memory resources (BRAM). For this purpose, an optimized memory access schema, that allows the best performance of the architecture with the least use of hardware resources, is proposed. Details of the design and the implementation on a Zynq UltraScale+ MPSoC are given, as well as speed-performance and area utilization. The proposed solution significantly improves the results achieved using this schema compared with those obtained using the Resize function from the Xilinx OpenCV library, when both are configured to obtain the same spatial transformation.es_ES
dc.description.sponsorshipThis work has been partially funded by Spanish government projects RTI2018-097088-B-C33 and TEC2015-66878-C3-2-R (MINECO/FEDER, UE).es_ES
dc.formatapplication/pdfes_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.titleEfficient VHDL Implementation of an Upscaling Function for Real Time Video Applicationses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.subjectFPGAes_ES
dc.subjectResize
dc.subjectOptimized Memory Access
dc.subjectUpscaling
dc.subjectBRAM
dc.subject.otherArquitectura y Tecnología de Computadorases_ES
dc.subject.otherElectrónicaes_ES
dc.identifier.urihttp://hdl.handle.net/10317/8320
dc.peerreviewSi
dc.identifier.doi10.1109/ISCAS.2019.8702453
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8702453
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES
dc.relation.projectIDRTI2018-097088-B-C33es_ES
dc.relation.projectIDTEC2015-66878-C3-2-Res_ES
dc.contributor.funderFondo Europeo de Desarrollo Regionales_ES
dc.contributor.funderMinisterio Economía y Empresaes_ES
dc.contributor.funderComisión Europeaes_ES


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