Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications
Compartir
Estadísticas
Ver Estadísticas de usoMetadatos
Mostrar el registro completo del ítemÁrea de conocimiento
Arquitectura y Tecnología de Computadoras; ElectrónicaPatrocinadores
This work has been partially funded by Spanish government projects RTI2018-097088-B-C33 and TEC2015-66878-C3-2-R (MINECO/FEDER, UE).Fecha de publicación
2019-05-28Editorial
IEEECita bibliográfica
RUBIO IBÁÑEZ, Pablo; MARTÍNEZ ÁLVAREZ, José Javier y DOMÉNECH ASENSI, Ginés. Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications. En: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5. doi: 10.1109/ISCAS.2019.8702453Revisión por pares
SiPalabras clave
FPGAResize
Optimized Memory Access
Upscaling
BRAM
Resumen
This paper describes the design and the implementation of a high-performance area-efficient upscaling function on a FPGA. The proposed function performs the resizing of real time video images, from M x N pixels to 2M x 2N pixels, using a bilinear interpolation method. The hardware implementation has been carried out using an RTL structural description in VHDL, to maximize the use of the specific resources of the FPGA, especially its memory resources (BRAM). For this purpose, an optimized memory access schema, that allows the best performance of the architecture with the least use of hardware resources, is proposed. Details of the design and the implementation on a Zynq UltraScale+ MPSoC are given, as well as speed-performance and area utilization. The proposed solution significantly improves the results achieved using this schema compared with those obtained using the Resize function from the Xilinx OpenCV library, when both are configured to obtain the same spatial transformation.
Colecciones
El ítem tiene asociados los siguientes ficheros de licencia:
Redes sociales