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dc.contributor.authorDoménech Asensi, Ginés 
dc.contributor.authorGarrigós Guerrero, Francisco Javier 
dc.contributor.authorLópez Martínez, Paula 
dc.contributor.authorBrea Sánchez, Víctor Manuel 
dc.contributor.authorCabello Ferrer, Diego
dc.identifier.citationDoménech Asensi, Ginés et al. Real time architectures for the scale Invariant feature transform algorithm. En: CNNA 2016. (15º. 2016.); 15th International Workshop on Cellular Nanoscale Networks and their Applications: 23-25 Aug. 2016. Berlin: VDE Verlag GmbH 2016.p. 75-76. ISBN: 978-3-8007-4252-3es_ES
dc.description.abstractFeature extraction in digital image processing is a very intensive task for a CPU. In order to achieve real time image throughputs, hardware parallelism must be exploited. The speed-up of the system is constrained by the degree of parallelism of the implementation and this one at the same time, by programmable device size and the power dissipation. In this work, issues related to the synthesis of the Scale-Invariant Feature Transform (SIFT) algorithm on a FPGA to obtain target processing rates faster than 50 frames per second for VGA images, are analyzed. In order to increase the speedup of the algorithm, the work includes the analysis of feasible simplifications of the algorithm for a tracking application and the results are synthesized on an FPGA.es_ES
dc.description.sponsorshipThis work has been partially funded by Spanish government projects TEC2015-66878-C3-2-R (MINECO/FEDER, UE) and TEC2015- 66878-C3-3-R (MINECO/FEDER, UE).es_ES
dc.publisherVDE Verlag GmbHes_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights© Copyright 2017 IEEEes_ES
dc.titleReal time architectures for the scale Invariant feature transform algorithmes_ES
dc.subjectScale invariant feature transformes_ES
dc.subject.unesco2209.90 Tratamiento Digital. Imágeneses_ES

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Except where otherwise noted, this item's license is described as Atribución-NoComercial-SinDerivadas 3.0 España