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dc.contributor.authorVillarejo Mañas, José Antonio 
dc.contributor.authorSebastián Zúñiga, Francisco Javier 
dc.contributor.authorSoto Vallés, Fulgencio 
dc.date.accessioned2009-01-29T09:08:46Z
dc.date.available2009-01-29T09:08:46Z
dc.date.issued2007-06
dc.identifier.citationVILLAREJO , José A., SEBASTIAN, Javier, SOTO, Fulgencio, JÓDAR, Esther de. Optimizing the design of single-stage power factor correctors. IEEE Transactions on Industrial Electronics , 54 (3): 1472-1482, Junio 2007. ISSN 0278-0046es
dc.identifier.issn0278-0046
dc.description.abstractThis paper presents a new analytical method for the generalized study of a cluster of single-stage power-factor correctors (S2PFCs). Due to this generalized approach, new topologies have been obtained, and the study of other known topologies has been simplified. The new analytical method simplifies the design of S2PFCs by making it possible to compare a large number of different designs from the same viewpoint in order to identify the best topology. Finally, this research has enabled us to reduce the total size of the additional inductors that are used by a factor of two to three with respect to previous implementations.es
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dc.language.isoenges
dc.publisherIEEE Industrial Electronics Societyes
dc.rightsCopyright © 2007 IEEEes
dc.titleOptimizing the design of single-stage power factor correctorses
dc.typeinfo:eu-repo/semantics/articlees
dc.subjectArmónicos actualeses
dc.subjectNormas IEC 61000-3-2es
dc.subjectCargas no linealeses
dc.subjectCorrección del factor de potencia (PFC)es
dc.subject.otherTecnología Electrónicaes
dc.identifier.urihttp://hdl.handle.net/10317/653
dc.contributor.investgroupDivisión de Sistemas e Ingeniería Electrónica (DSIE)es
dc.identifier.doi10.1109/TIE.2007.894734


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