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dc.contributor.authorDoménech Asensi, Ginés 
dc.contributor.authorLópez Alcantud, José Alejandro 
dc.contributor.authorRuiz Merino, Ramón Jesús 
dc.date.accessioned2010-11-12T13:35:01Z
dc.date.available2010-11-12T13:35:01Z
dc.date.issued2005-06-30
dc.identifier.citationDOMÉNECH ASENSI, Ginés, LÓPEZ ALCANTUD, José Alejandro, RUIZ MERINO, Ramón. Simulation-based low-level optimization tool for analog integrated circuits. En: VLSI Circuits and Systems II (2005: Sevilla). Proceedings of SPIE: VLSI Circuits and Systems II. Sevilla. 2005. vol. 5837, 685-692 p. ISBN 9780819458322es
dc.identifier.isbn9780819458322
dc.description.abstractIn this paper, a tool based on free software to perform low level optimization on analog designs is presented. Nowadays, the use of design automation tools for microelectronic circuits design is extending from digital to analog circuits, due in part to the fact although the analog part of a mixed signal ASIC takes only the 10% of the silicona area, it represents almost 90% of the whole design time. For analog circuits, design process can be divided in two major tasks: topology selection an device sizing. The tool here presented consists on a simulation based optimizer, which is used to perform automatic low level analog circuit sizing. The tool is composed of three modules: a layout generator, which includes a parasitic extractor, an analog circuit simulator and circuit optimizer. The two first modules are respectively Mgic and Spice from Berkeley, while the third one, the optimizer, has been developed to evaluate dc, ac, and transient sensitivity simulations performed by Spice and make corrections on the layout sizing. Optimization process atars with a certain topology and atandard sized devices, which is then extracted by Magic and simulated by Spice. Performance is evaluated and a sizing correction is proposed. These simulations and corrections are done on an iteractive loop until circuit performance reaches design parameters. The tool is demonstrated with an example of a simple analog subcircuit optimization, where parameters like silicon area or power dissipation are optimized, while the circuit keeps on design parameterses
dc.description.sponsorshipThis work has been supported by Fundación Séneca of Región de Murcia and Ministerio de Ciencia y Tecnología od Spain, under grants PB/63/FS/02 and TIC2003-09400-C04-02, respectively.es
dc.formatapplication/pdf
dc.language.isoenges
dc.publisherSPIEes
dc.rightsCopyright © 2005 SPIEes
dc.titleSimulation-based low-level optimization tool for analog integrated circuitses
dc.typeinfo:eu-repo/semantics/conferenceObjectes
dc.subjectAutomatización de diseño electrónicoes
dc.subjectCircuito de optimizaciónes
dc.subjectSpicees
dc.subjectCMOS analog integrated circuitses
dc.subjectElectronic design automationes
dc.subjectCircuit optimizationes
dc.subjectCircuitos integrados analógicos CMOS
dc.subject.otherElectrónicaes
dc.identifier.urihttp://hdl.handle.net/10317/1415
dc.contributor.investgroupDispositivos y Diseño Microelectrónicoes
dc.contributor.investgroupDiseño Electrónico y Técnicas de Tratamiento de Señales
dc.identifier.doi10.1117/12.608724


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