Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing
Autor
Neubauer, Harald; Doménech Asensi, Ginés; Ruiz Merino, Ramón Jesús; Díaz Madrid, José Ángel; Hauer, HansÁrea de conocimiento
ElectrónicaPatrocinadores
This work has been supported by Ministerio de Educación y Ciencia of Spain and the European Regional Development Fund of the European Commission (FEDER) under grant TIN2006-15460-C04-04)Fecha de publicación
2009-04Editorial
Institute Electrical and Electronics Engineers (IEEE)Cita bibliográfica
DÍAZ MADRID. J.A., NEUBAUER, H., HAUER, H., DOMÉNECH ASENSI, G., RUIZ MERINO, R. Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. En: Design, Automation & Test in Europe Conference & Exhibition (2009: Niza, Francia). Proceedings: Design, Automation and Test in Europe. Nice, France, April 20-24, 2009. Niza: Institute Electrical and Electronics Engineers. 2009. 1530-1591 p. ISBN 978-1-4244-3781-8Palabras clave
ADCCMOS
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Resumen
High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35 mum CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one.
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