An efficient numerical solution technique for VLSI interconnect equations on many-core processors
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Desarrollo de sistemas y circuitos electrónicos y microelectrónicosÁrea de conocimiento
ElectrónicaPatrocinadores
This work has been partially funded by Spanish government through projects RTI2018-097088-B-C33 and TEC2015-66878-C3-2-R (MINECO/FEDER, UE), by EPSRC (the UK Engineering and Physical Sciences Research Council) under grant EP/N0317681/1 and by Universidad Politécnica de Cartagena - Campus de Excelencia Internacional Mare Nostrum. The research stay at University of Southampton (UK) has been supported by Ministerio de Educación, Cultura y Deporte within the “Programa Estatal de Promoción del Talento y su Empleabilidad en I+D+i, Subprograma Estatal de Movilidad, del Plan Estatal de I+D+I” under grant PRX18/00565.Realizado en/con
University of Southampton (UK)Fecha de publicación
2019-05-31Editorial
IEEECita bibliográfica
DOMÉNECH ASENSI, Ginés y KAZMIERSKI, Tom J. An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors. En: IEEE International Symposium on Circuits and Systems (ISCAS), 2019, pp. 1-5, doi: 10.1109/ISCAS.2019.8702085Revisión por pares
SíPalabras clave
Simulation accelerationState-space technique
GPU
VLSI interconnect
Resumen
This paper presents a technique to accelerate transient simulations of analog circuits using an explicit
integration method parallelised on a many-core computer. Usual methods used by SPICE-type simulators are based on
Newton–Raphson iterations, which are reliable and numerically stable, but require long CPU processing times. However,
although the integration time step in explicit methods is smaller than that used in implicit methods, this technique avoids
the calculation of time-consuming computations due to the Jacobian matrix inversion. The proposed method uses an explicit
integration scheme based on the fourth order Adams–Bashforth formula. The algorithm has been parallelised on a NVIDIA
general purpose GPU using the CUDA programming model. As a case study, the RC ladder model of a VLSI interconnect
is simulated on a general purpose graphic processing unit and the achieved performance is then evaluated against that of a
multiprocessor CPU. The results show that the ...
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