Hardware implementation of a controller based on neurobiological adaptive models of the human motor-control system
Author
Martínez Álvarez, José Javier; Guerrero González, Antonio; Pedreño Molina, Juan Luis; Villaescusa Fernández, Antonio; Ferrández Vicente, José Manuel; [et al.]Research Group
Grupo de Neurotecnología, Control y Robótica. (NEUROCOR)Grupo de Electromagnetismo y Materia (GEM)Knowledge Area
Arquitectura y Tecnología de ComputadorasIngeniería de Sistemas y AutomáticaTeoría de la Señal y las ComunicacionesPublication date
2002-10Publisher
Institute Electrical and Electronics Engineers (IEEE)Bibliographic Citation
MARTÍNEZ ÁLVAREZ, José Javier et al. Hardware implementation of a controller based on neurobiological adaptive models of the human motor-control system. En: IEEE International Conference on Systems, Man and Cybernetics (2002: Yasmine Hammamet - Tunisia). IEEE International Conference on Systems, Man and Cybernetics: Bridging the Digital Divide , Cyber-development, Human Progress, Peace and Prosperity. Yasmine Hammamet - Tunisia, October 6-9, 2002. Conference Proceedings. [Piscataway]: IEEE. 2002, vol.5, p. 3. ISBN 0-7803-7437-1Keywords
NeurocontrollerRobotic
Neural device
Neurocontrolador
Robótica
Dispositivos neuronales
Abstract
In this work, a neural structure has been implemented into a device based on the new trends in hardware integration, for motor-control In multisensorial anthropomorphic robotic systems. This implementation gives a solution to the problem of physic integration of biologically Inspired control hierarchies in a robotic head-arm installation for robotic reaching tasks. The complete architecture has been implemented on an electronic board connected to a PC computer through a PCI interface. The hardware structure consists of two blocks: one for the working phase of the system, and the other for the learning and supervision phase of the system. These two blocks have been implemented with different technologies based on DSP processors and FPGAs. The algorithms implemented on DSPs have the function of updating the neural network on the FPGA, supervising the working of the algorithm implemented on FPGA and introducing corrections when the neural network produces results with little errors. The ...
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