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dc.contributor.authorDoménech Asensi, Ginés 
dc.contributor.authorRuiz Merino, Ramón Jesús 
dc.contributor.authorZapata Pérez, Juan Francisco 
dc.contributor.authorLópez Alcantud, José Alejandro 
dc.contributor.authorDíaz Madrid, José Ángel 
dc.date.accessioned2018-02-23T13:41:44Z
dc.date.available2018-02-23T13:41:44Z
dc.date.issued2017
dc.identifier.citationDOMÉNECH ASENSI, Ginés et al. FPGA synthesis of an stereo image matching architecture for autonomous mobile robots. En: XXXII Conference on Design of Circuits and Integrated Systems, DCIS 2017, Barcelona, 22 a 24 de noviembre ,2017es_ES
dc.description.abstractThis paper describes a hardware proposal to speed up the process of image matching in stereo vision systems like those employed by autonomous mobile robots. This proposal combines a classical window-based matching approach with a previous stage, where key points are selected from each image of the stereo pair. In this first step the key point extraction method is based on the SIFT algorithm. Thus, in the second step, the window-based matching is only applied to the set of selected key points, instead of to the whole images. For images with a 1% of key points, this method speeds up the matching four orders of magnitude. This proposal is, on the one hand, a better parallelizable architecture than the original SIFT, and on the other, a faster technique than a full image windows matching approach. The architecture has been implemented on a lower power Virtex 6 FPGA and it achieves a image matching speed above 30 fps.es_ES
dc.description.sponsorshipThis work has been funded by Spanish government project TEC2015-66878-C3-2-R (MINECO/FEDER, UE).es_ES
dc.formatapplication/pdfes_ES
dc.language.isoenges_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.titleFPGA synthesis of an stereo image matching architecture for autonomous mobile robotses_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.subject.otherElectrónicaes_ES
dc.subjectComputer visiones_ES
dc.subjectStereo visiones_ES
dc.subjectSIFTes_ES
dc.subjectSADes_ES
dc.subjectFPGAes_ES
dc.identifier.urihttp://hdl.handle.net/10317/6605
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES
dc.type.versioninfo:eu-repo/semantics/submittedVersiones_ES
dc.relation.projectIDTEC2015-66878-C3-2-Res_ES
dc.subject.unesco2203 Electrónicaes_ES


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Atribución-NoComercial-SinDerivadas 3.0 España
Except where otherwise noted, this item's license is described as Atribución-NoComercial-SinDerivadas 3.0 España