Design and analysis of efficient synthesis algorithms for EDAC functions in FPGAs
Patrocinadores
This work was supported by the Spanish Ministry of Educacion, Cultura y Deporte under the grant FPU12/05573, and by the Spanish Ministry of Economıa project ESP2013-48362-C2-2-P, in the frame of the activities of the Instrument Control Unit of the Infrarred Instrument of the ESA Euclid Mission carried out by the Dept. of Electronics and Computer Technology of the Universidad Politécnica de CartagenaFecha de publicación
2015-10Editorial
Institute of Electrical and Electronics Engineers (IEEE)Cita bibliográfica
COLODRO CONDE, Carlos, TOLEDO MOREO, Rafael. Design and analysis of efficient synthesis algorithms for EDAC functions in FPGAs. En: IEEE Transactions on Aerospace and Electronic Systems, vol. 51, n. 4, p. 3332 - 3347, 2015. ISSN: 0018-9251Revisión por pares
SiPalabras clave
Field programmable gate arrays (FPGA)Synthesis tools
Efficient synthesis
Error detection and correction (EDAC)
Single event upsets (SEU)
Resumen
Error Detection and Correction (EDAC) functions have been widely used for protecting memories from single event upsets (SEU), which occur in environments with high levels of radiation or in deep submicron manufacturing technologies. This paper presents three novel synthesis algorithms that obtain areaefficient implementations for a given EDAC function, with the ultimate aim of reducing the number of sensitive configuration bits in SRAM-based Field-Programmable Gate Arrays (FPGAs). Having less sensitive bits results in a lower chance of suffering a SEU in the EDAC circuitry, thus improving the overall reliability of the whole system. Besides minimizing area, the proposed algorithms also focus on improving other figures of merit like circuit speed and power consumption. The executed benchmarks show that, when compared to other modern synthesis tools, the proposed algorithms can reduce the number of utilized look-up tables (LUTs) up to a 34.48%. Such large reductions in area usage ultimately ...
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