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Discrete-time cellular neural networks in FPGA
dc.contributor.author | Martínez Álvarez, José Javier | |
dc.contributor.author | Ferrández Vicente, José Manuel | |
dc.contributor.author | Toledo Moreo, Francisco Javier | |
dc.date.accessioned | 2010-11-12T13:44:28Z | |
dc.date.available | 2010-11-12T13:44:28Z | |
dc.date.issued | 2007-04 | |
dc.identifier.citation | MARTÍNEZ ÁLVAREZ, José Javier; FERRÁNDEZ VICENTE, José Manuel y TOLEDO MOREO, Francisco Javier. Discrete-time cellular neural networks in FPGA. En: Annual IEEE Symposium on Field-Programmable Custom Computing Machines (15º: 2007: Napa, California) 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007. 23-25 April 2007 Napa, California. Los Alamitos, California: IEEE Computer Society, 2007. Pp. 293-294. ISBN 978-0-7695-2940-0 | es |
dc.identifier.isbn | 978-0-7695-2940-0 | |
dc.description.abstract | This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions of neurons accommodated in low price FPGA devices, being able to process standard video in real time. | es |
dc.description.sponsorship | This research has been funded by MTyAS of Spain, IMSERSO RETVIS 150/06. | es |
dc.format | application/pdf | |
dc.language.iso | eng | es |
dc.publisher | IEEE Computer Society | es |
dc.rights | Copyright © 2007 IEEE | es |
dc.title | Discrete-time cellular neural networks in FPGA | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dc.subject.other | Arquitectura y Tecnología de Computadoras | es |
dc.subject | Arquitectura de hardware | es |
dc.subject | Sistemas de tiempo discreto | es |
dc.subject | Campo de las matrices de puerta programable | es |
dc.subject | Perceptrones multicapa | es |
dc.subject | Chip neuronales | es |
dc.subject | Arquitectura de red neuronal | es |
dc.subject | FPGA | es |
dc.subject | Hardware arquitecture | es |
dc.subject | Discrete time system | es |
dc.subject | Field programmable gate array | es |
dc.subject | Multilayer perceptron | es |
dc.subject | Neural chip | es |
dc.subject | Neural net architecture | es |
dc.identifier.uri | http://hdl.handle.net/10317/1421 | |
dc.contributor.investgroup | Grupo de Diseño Electrónico y Técnicas de Tratamiento de señal | es |
dc.identifier.doi | 10.1109/FCCM.2007.25 |
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