TY - JOUR 
A1 - Neubauer, Harald
AU - Doménech Asensi, Ginés
AU - Ruiz Merino, Ramón Jesús
AU - Díaz Madrid, José Ángel
AU - Hauer, Hans
T1 - Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing
Y1 - 2009
UR - http://hdl.handle.net/10317/1256
AB - High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35 mum CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one.
KW - Electrónica
KW - ADC
KW - CMOS
KW - Baja potencia
KW - Línea de tuberia
LA - eng
PB - Institute Electrical and Electronics Engineers (IEEE)
ER -