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dc.contributor.authorDíaz Madrid, José Ángel 
dc.contributor.authorDoménech Asensi, Ginés 
dc.contributor.authorLópez Alcantud, José Alejandro 
dc.contributor.authorOberst, Matthias 
dc.date.accessioned2018-02-23T13:41:56Z
dc.date.available2018-02-23T13:41:56Z
dc.date.issued2017
dc.identifier.citationDÍAZ MADRID, José Ángel et al. An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. En: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017. pages 1-4, IEEE, 2017es_ES
dc.identifier.isbn978-1-4673-6853-7
dc.identifier.issn2379-447X
dc.description.abstractThis paper presents a pipeline analog to digital converter (ADC) consisting of five stages with 2.5 effective bit resolution. Several techniques were combined for the reduction of the power consumption and to preserve the converter linearity. To reduce the power consumption, the circuit has two scaled operational transconductance amplifiers (OTAs), which are shared by the first four pipeline stages. The last fifth stage is a single decoder with 2.5 effective bits. Each OTA includes additional circuitry to adapt the power consumption according to the stage that uses the OTA. This technique changes the bias current depending on the stage in operation. The ADC was optimized to obtain 11-bit resolution with frequencies from 1 kHz to 10 MHz. The technology used to simulate the ADC is a 3.3 V 0.35 μm CMOS process and the circuit consumes 17.9 mW at 20 MSample/s sampling rate. With this resolution and sampling rate, it achieves 67.28 dB SNDR and 10.88 bit ENOB at 0.1 MHz input frequency. The Figure of Merit is 0.473 pJ/stepes_ES
dc.description.sponsorshipThis work has been partially funded by Spanish government project TEC2015-66878-C3-2-R (MINECO/FEDER, UE).es_ES
dc.formatapplication/pdfes_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.rightsAtribución-NoComercial-SinDerivadas 3.0 España*
dc.rights© Copyright 2017 IEEEes_ES
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/*
dc.rights.urihttp://ieeexplore.ieee.org/document/8050484/?reload=truees_ES
dc.titleAn 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipationes_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.subject.otherElectrónicaes_ES
dc.subjectAnalog-to-digital converter (ADC)es_ES
dc.subjectPipelinees_ES
dc.subjectCMOSes_ES
dc.subjectOTAes_ES
dc.subjectOp-amp sharinges_ES
dc.subjectLow poweres_ES
dc.identifier.urihttp://hdl.handle.net/10317/6606
dc.rights.accessRightsinfo:eu-repo/semantics/openAccesses_ES
dc.type.versioninfo:eu-repo/semantics/submittedVersiones_ES
dc.relation.projectIDTEC2015-66878-C3-2-Res_ES
dc.subject.unesco2203 Electrónicaes_ES


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