Design considerations for single-stage, input- current shapers for low output voltage ripple
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Research GroupDivisión de Sistemas e Ingeniería Electrónica (DSIE)
Knowledge AreaTecnología Electrónica
PublisherInstitute Electrical and Electronics Engineers. (IEEE)
Bibliographic CitationVILLAREJO, José, SEBASTIÁN, Javier, SOTO, Fulgencio. Design considerations for single-stage, input- current shapers for low output voltage ripple. En: Annual IEEE Applied Power Electronics Conference and Exposition (20ª : 2005: Austin, Texas). Applied Power Electronics Conference and Exposition, 2005. APEC 2005. Twentieth Annual IEEE. Volume 2, 6-10 Marzo 2005. Austin,Texas: IEEE, 2005. 1158-1162p. DOI 10.1109/APEC.2005.1453144
A lot of power topologies have been proposed to comply with the IEC-61000-3-2 regulations. One group of solutions involves obtaining an additional output from one of the converter’s magnetic devices. These solutions are very good due to the low harmonic content and from the low cost point of view. Nevertheless these magnetic coupled circuits can modify the converter’s performance. The abnormal operation can be observed as an output voltage ripple higher than expected. This paper deals with the design considerations for law output voltage ripple Single-Stage-Input-Current Shapers (S’ICS) and explains the abnormalities.
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