A multi-FPGA distributed embedded system for the emulation of Multi-Layer CNNs in real time video applications
View/ Open
Share
Statistics
View Usage StatisticsMetadata
Show full item recordAuthor
Ferrández Vicente, José Manuel; Toledo Moreo, Francisco Javier; Martínez Álvarez, José Javier; Garrigós Guerrero, Francisco JavierResearch Group
Grupo de Diseño Electrónico y Técnicas de Tratamiento de señalKnowledge Area
Arquitectura y Tecnología de ComputadorasSponsors
This work has been partially supported by the Fundación Séneca de la Región de Murcia through the research projects 08801/PI/08 and 08788/PI/08, and by the Spanish Government through project TIN2008-06893-C03.Publication date
2010-03-29Publisher
Institute Electrical and Electronics Engineers (IEEE)Bibliographic Citation
FERRÁNDEZ VICENTE, José Manuel et al. A multi-FPGA distributed embedded system for the emulation of Multi-Layer CNNs in real time video applications. En: International Workshop on Cellular Nanoscale Networks and Their Applications (12º: 2010: Berkeley, CA ) 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA), 2010. Berkeley, CA : Institute Electrical and Electronics Engineers. 2010. Pp. 1-5. ISBN 978-1-4244-6679-5Keywords
Componente de palabras claveMulti-FPGA
Sistemas incrustados
Emulación CNN
Keywords-component
Embedded systems
Emulation CNN
Abstract
This paper describes the design and the implementation of an embedded system based on multiple FPGAs that can be used to process real time video streams in standalone mode for applications that require the use of large Multi-Layer CNNs (ML-CNNs). The system processes video in progressive mode and provides a standard VGA output format. The main features of the system are determined by using a distributed computing architecture, based on Independent Hardware Modules (IHM), which facilitate system expansion and adaptation to new applications. Each IHM is composed by an FPGA board that can hold one or more CNN layers. The total computing capacity of the system is determined by the number of IHM used and the amount of resources available in the FPGAs. Our architecture supports traditional cloned templates, but also the (simultaneous) use of time-variant and space-variant templates.
Collections
The following license files are associated with this item:
Social media