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Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing
dc.contributor.author | Neubauer, Harald | |
dc.contributor.author | Doménech Asensi, Ginés | |
dc.contributor.author | Ruiz Merino, Ramón Jesús | |
dc.contributor.author | Díaz Madrid, José Ángel | |
dc.contributor.author | Hauer, Hans | |
dc.date.accessioned | 2010-05-17T07:20:47Z | |
dc.date.available | 2010-05-17T07:20:47Z | |
dc.date.issued | 2009-04 | |
dc.identifier.citation | NEUBAUER, Harald et al. Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. En: Design, Automation & Test in Europe Conference & Exhibition (2009: Niza, Francia). Proceedings: Design, Automation and Test in Europe. Nice, France, April 20-24, 2009. Niza: Institute Electrical and Electronics Engineers, 2009. Pp. 1530-1591. ISBN 978-1-4244-3781-8 | es |
dc.identifier.isbn | 978-1-4244-3781-8 | |
dc.description.abstract | High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35 mum CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one. | es |
dc.description.sponsorship | This work has been supported by Ministerio de Educación y Ciencia of Spain and the European Regional Development Fund of the European Commission (FEDER) under grant TIN2006-15460-C04-04) | es |
dc.format | application/pdf | |
dc.language.iso | eng | es |
dc.publisher | Institute Electrical and Electronics Engineers (IEEE) | es |
dc.rights | Copyright © 2009 IEEE | es |
dc.title | Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing | es |
dc.type | info:eu-repo/semantics/conferenceObject | es |
dc.subject.other | Electrónica | es |
dc.subject | ADC | es |
dc.subject | CMOS | es |
dc.subject | Baja potencia | es |
dc.subject | Línea de tuberia | es |
dc.identifier.uri | http://hdl.handle.net/10317/1256 |
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