Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS
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SponsorsThis work has been partially supported by Fundación Séneca of Región de Murcia(Ref:03094/PI/05)and MEC of Spain(Ref:TIN2006-15460-C04-04).
PublisherInstitute Electrical and Electronics Engineers (IEEE)
Bibliographic CitationDÍAZ MADRID, José Ángel, NEUBAUER, Harald, DOMENECH ASENSI, Ginés, RUIZ, Ramón. Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS. En: IEEE International Conference on Integrated Circuit Design and Technology (2008: Greboble, France). IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT 2008. Grenoble, France: Institute Electrical and Electronics Engineers. 2008. 121 - 124 p. ISBN 978-1-4244-1810-7
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This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for low power dissipation. All analog components of this pipeline ADC are fully differential, as there are dynamic comparators, analog multiplexers and operational amplifiers with gain boosting.
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