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dc.contributor.authorAlonso Cáceres, Diego 
dc.contributor.authorVicente Chicote, Cristina 
dc.contributor.authorPastor Franco, Juan Ángel 
dc.contributor.authorÁlvarez Torres, María Bárbara 
dc.date.accessioned2010-03-12T07:57:56Z
dc.date.available2010-03-12T07:57:56Z
dc.date.issued2008-06-11
dc.identifier.citationALONSO, Diego, VICENTE CHICOTE, Cristina, PASTOR, Juan A., ÁLVAREZ, Bárbara. StateML + : From Graphical State Machine Models to Thread-Safe Ada Code. Lecture Notes in Computer Science, 5026/2008: 158-170, Junio 2008. ISSN 0302-9743es
dc.identifier.issn0302-9743
dc.description.abstractThis paper presents the StateML+ tool aimed at designing state-machines and automatically generating thread-safe and multi-tasking modular Ada code from them, following a Model-Driven Engineering approach. The StateML+ meta-model is an extension of a previous version, and now it offers improved modeling capabilities, which include regions and macro-state definition. In this paper, a case study regarding the design of a robotic system will be used to demonstrate the benefits of the proposed approach.es
dc.description.sponsorshipThis research has been funded by the Spanish CICYT project MEDWSA (TIN2006-15175-C05-02) and the Regional Government of Murcia Seneca Program (02998-PI-05).es
dc.formatapplication/pdf
dc.language.isoenges
dc.publisherSpringeres
dc.rightsCopyright © 2008 Springeres
dc.rightsThe original publication is available at www.springerlink.comes
dc.titleStateML + : From Graphical State Machine Models to Thread-Safe Ada Codees
dc.typeinfo:eu-repo/semantics/articlees
dc.subject.otherLenguajes y Sistemas Informáticoses
dc.subjectModelos de Ingeniería de conducciónes
dc.subjectTransformación de modelo a textoes
dc.subjectMáquinas de estado finitoes
dc.subjectGeneración de hilo seguro de códigoes
dc.subjectPlataforma eclipsees
dc.subjectModel driven engineering (MDE)es
dc.subjectModel to text transformationes
dc.subjectFinite state machines (FSM)es
dc.subjectThread safe code generationes
dc.subjectEclipse platformes
dc.identifier.urihttp://hdl.handle.net/10317/1217
dc.contributor.investgroupDivisión de Sistemas e Ingeniería Electrónica (DSIE)es
dc.identifier.doi10.1007/978-3-540-68624-8_12


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