%0 Journal Article %A Neubauer, Harald %A Doménech Asensi, Ginés %A Ruiz Merino, Ramón Jesús %A Díaz Madrid, José Ángel %A Hauer, Hans %T Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing %D 2009 %U http://hdl.handle.net/10317/1256 %X High performance analog-to-digital converters (ADC) are essential elements for the development of high performance image sensors. These circuits need a big number of ADCs to reach the required resolution at a specified speed. Moreover, nowadays power dissipation has become a key performance to be considered in analog designs, specially in those developed for portable devices. Design of such circuits is a challenging task which requires a combination of the most advanced digital circuit, the analog expertise knowledge and an iterative design. Amplifier sharing has been a commonly used technique to reduce power dissipation in pipelined ADCs. In this paper we present a partial amplifier sharing topology of a 12 bit pipeline ADC, developed in 0.35 mum CMOS process. Its performance is compared with a conventional amplifier scaling topology and with a fully amplifier sharing one. %K Electrónica %K ADC %K CMOS %K Baja potencia %K Línea de tuberia %~ GOEDOC, SUB GOETTINGEN